Liquid crystal display, referred to as LCD (Liquid Crystal Display), compared with the previous generation CRT display (cathode ray tube display), LCD display has the advantages of low power consumption, small size, large amount of information carried and no eye damage, so it has become a The current mainstream electronic display devices, including TVs, computer monitors, mobile phone screens and displays of various embedded devices. .
Liquid crystal is a special substance between solid and liquid. It is an organic compound. It is liquid in normal state, but its molecular arrangement is as regular as that of solid crystal, so it is named liquid crystal. If an electric field is applied to the liquid crystal, its molecular arrangement will be changed, thereby changing the propagation direction of the light. With the polarizer, it has the function of controlling the light transmittance, and then with the color filter, the voltage applied to the liquid crystal can be changed. You can change the amount of light transmission of a certain color. The green display structure is shown in Figure 1.1. Using this principle, a display structure that can control the output intensity of red, green and blue light is made, and the three display structures are combined into a display unit. By controlling the intensity of red, green and blue, the unit can be mixed to output different colors. A display unit is called a pixel.(Display units are called pixels.)
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| Fig 1 Liquid Crystal Technology Layer |
Note that the liquid crystal itself does not emit light, so a backlight needs to be provided to provide the light source, and the light is output after a series of processing processes, so the output light intensity is much lower than that of the light source, Moreover, these processing processes will result in a relatively narrow display direction, that is, its viewing angle is small, and its display content cannot be clearly seen from the side of the screen. In addition, when the output color is changed, the rotation of the liquid crystal molecules also takes a certain amount of time, resulting in a low response speed of the screen.
The LED dot matrix display does not have the above problems of the liquid crystal display. A single pixel of the LED dot matrix color display contains three-color LED lights of red, green and blue. The display principle is similar to the LED lights on our experimental board. The intensity is mixed to achieve full-color color output, and multiple pixels form a screen. Since each pixel is self-illuminated by LED lights, it can be displayed very clearly in the daytime outdoors. However, due to the large size of the LED lights, the pixel density of the screen is low, so it is generally only suitable for giant displays in squares. . Relatively speaking, single-color LED dot matrix displays are widely used, such as information display boards on buses, store signs, etc., a
The new generation of OLED display is similar to the principle of LED dot matrix color display, but because the pixel unit it uses is "Organic Light Emitting Diode", the pixel density is much higher than that of ordinary LED dot matrix display.
LED displays do not require a backlight, have high contrast ratios, are thin and light, have wide viewing angles, and have fast response times. When the production process is more mature, it will definitely replace the current status of the liquid crystal display.
Liquid crystal control principle
Figure 2 shows two types of display screens suitable for STM32 chips. We take it as an example to explain the basic principle of controlling the LCD screen
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Fig 2 Display Difference |
This complete display consists of an LCD panel, a capacitive touch panel, and a PCB backplane. The touch panel in the picture has a touch control chip, which processes touch signals and communicates with external devices through the drawn signal lines. The middle of the touch panel is transparent, and it is attached to the liquid crystal panel to form the main body of the screen. The touch panel and the The cables drawn from the LCD panel are connected to the PCB backplane. According to actual needs, the PCB backplane may have an "LCD controller chip". The LCD screen PCB on the right in the figure has an RA8875 LCD controller. Because controlling the LCD panel requires more resources, most low-level microcontrollers cannot directly control the LCD panel, and an additional dedicated LCD controller is required to handle the display process. The external microcontroller only needs to send the data it wants to display directly to the Just give it to the LCD controller. Instead of a PCB backplane with an LCD controller, there is only a small part of the power management circuit, and the signal line of the LCD panel is connected to an external microcontroller for direct control.
NOTE : The STM32F429 series of chips do not require an additional LCD controller, which means that it integrates the functions of the dedicated LCD controller into the STM32F429 chip, which can be understood as the computer's CPU integrated graphics card, which saves additional controller costs. Since the STM32F1 series chip does not integrate the LCD controller into the chip, it can only drive the screen with its own controller, which can be understood as the external graphics card of the computer. In general, the control block diagrams for these two types of screens are shown in Figure 3.
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| Fig 3 Display Unit Difference |
LCD panel control signal
We mainly explain how to control the LCD panel. The control signal lines of the LCD panel are the FPC cables drawn from the LCD panel , and the description is shown in Table 1. The LCD panel communicates with the LCD controller through these signal lines. This communication signal is called RGB Interface (RGB Interface).
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| TABLE 1 RGB INTERFACE |
1) RGB signal line
There are 8 RGB signal lines each, which are used to represent the red, green, and blue color components of a pixel of the LCD screen. It is a common practice to use red, green and blue color components to represent colors. Open the artboard color palette tool that comes with the Windows system, and you can see the red, green and blue component values of the color. The common color representation will be followed by "RGB" with the data bits of each color component value. For example, RGB565 indicates that the number of data lines for red, green and blue is 5, 6, and 5 respectively. There are 16 data bits in total, which can represent 2 16 There are 8 data lines for each color component of this LCD screen, so it supports RGB888 format, a total of 24 data lines, and 224 colors can be represented.
(2) Synchronous clock signal CLK
The LCD screen uses the synchronous communication method with the outside, and uses the CLK signal as the synchronous clock. Driven by the synchronous clock, each clock transmits one pixel data.
(3) Horizontal synchronization signal HSYNC
The horizontal synchronization signal HSYNC (Horizontal Sync) is used to indicate the end of the transmission of a line of pixel data on the LCD screen. When the transmission of a line of pixel data on the LCD screen is completed, the level of HSYNC will jump, such as a display screen with a resolution of 800x480 (800 columns). , 480 lines), the level of HSYNC will jump 480 times when transmitting one frame of image.
(4) Vertical synchronization signal VSYNC
The vertical synchronization signal VSYNC (Vertical Sync) is used to indicate the end of the transmission of one frame of pixel data on the LCD screen. When the transmission of one frame of pixel data is completed, the level of VSYNC will jump. where "frame" is the unit of the image, a frame
An image is called a frame, and in an LCD screen, a frame refers to a complete screen of LCD pixels. People often use "frames per second" to represent the refresh characteristics of the LCD screen, that is, how many frames of images the LCD screen can display per second. For example, when the LCD screen runs at a rate of 60 frames per second, the level of VSYNC will jump 60 per second. Second-rate.
(5) Data enable signal DE
The data enable signal DE (Data Enable) is used to indicate the validity of the data. When the DE signal line is at a high level, the data represented by the RGB signal line is valid.
LCD data transmission timing
When transmitting pixel data to the LCD screen through the above signal lines, the timing of each signal line is shown in Figure 4. The figure shows the time sequence of transmitting one frame of image data to the LCD screen, omitting multiple lines and multiple pixels in the middle.
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| Fig 4 Timing Data transmission |
The image displayed on the LCD screen can be seen as a rectangle, which can be understood in conjunction with Figure 5. The LCD screen has a display pointer that points to the pixel that will be displayed. The scanning direction of the display pointer is from left to right, from top to bottom, and the graphics are drawn pixel by pixel. The data of these pixels are transmitted to the LCD screen through the RGB data line, and they are transmitted to the LCD screen one by one under the drive of the synchronous clock CLK, and handed over to the display pointer. When the transmission is completed for one line, the level of the horizontal synchronization signal HSYNC jumps once , and the VSYNC level jumps once when a frame is transmitted.
However, the liquid crystal display pointer needs a delay when switching between lines and between frames, and the HSYNC and VSYNC signals themselves have a width.
In the area controlled by these time parameters, the data enable signal line "DE" is low, and the signal of the RGB data line is invalid. When "DE" is high, the indicated data is valid, and the transmitted data will directly affect the liquid crystal. display area of the screen.
video memory
Each pixel in the LCD screen is data. In practical applications, the data of each pixel needs to be cached and then transmitted to the LCD screen. Generally, SRAM or SDRAM memory is used, and these are specially used for storage and display. The memory for data is called video memory. Generally, the video memory should be able to store at least one frame of display data of the LCD screen. For example, if the LCD screen with a resolution of 800x480 is displayed in RGB888 format, the size of one frame of display data is: 3x800x480=1152000 bytes; if it is displayed in RGB565 format, a The frame display data size is: 2x800x480=768000 bytes. Generally speaking, the external LCD controller will have its own video memory, and chips with integrated LCD controller such as STM32F429 can use internal SRAM or external SDRAM for video memory space.
Resistive touch screen
The LCD controller and LCD screen of the screen explained above are completely separated, and there are versions with and without a controller, which is easy to understand. Let's analyze the standard 3.2-inch resolution of the experimental board with a resolution of 320*240. Resistive touch LCD screen, see Figure 27-11.
The part labeled 3 in the figure is the whole of the LCD screen, which can be controlled by connecting it to the experiment board through the pin headers. It is divided into two parts: the LCD touch panel labeled 1 and the PCB bottom plate labeled 2.
The LCD touch panel at number 1 is composed of an LCD screen and a touch screen. The gray wire frame on the screen surface is the signal line of the resistive touch screen, and the bottom of the touch screen is the LCD panel, which contains an LCD controller with a model of ILI9341. The chip (due to high integration, it cannot be seen in the picture), the LCD controller uses the 8080 interface to communicate with the single-chip microcomputer, and the FPC signal line drawn from the LCD panel in the picture is the 8080 interface (the RGB interface has been directly connected to the ILI9341 internally), and The controller contains video memory, the single-chip microcomputer sends the data to be displayed to the LCD controller through the 8080 interface, and these data will be stored in its internal video memory, and then the LCD controller continuously refreshes the content of the video memory to the LCD panel. Display content.
Number 2 is the PCB backplane, which mainly includes a resistive touch screen controller XPT2046. The resistive touch screen controller is essentially an ADC chip, which calculates the touch coordinates by detecting the voltage value. The PCB bottom plate and the LCD touch panel are connected through the FPC cable socket, and then lead out to the pin header, which is convenient for connecting with the female header of the experiment board.
In this chapter, we will take a 3.0-inch TFTLCD module as an example to introduce (other sizes of color screens and driver chips are used in a similar way). The module driver chip model is R61509V3, the resolution is 240*400, and the interface is a 16-bit 80 parallel port. With touch function. The appearance of the module is shown in Figure 38.1.1:
The TFTLCD module uses 2*17 2.54 male pin headers to connect to the outside. It can be seen from Figure 38.1.2 that this TFTLCD module uses a 16-bit parallel port to connect to the outside. The reason why the 8-bit method is not used is because the color screen The amount of data is relatively large, especially when displaying pictures, if an 8-bit data line is used, it will be more than twice as slow as the 16-bit mode. Of course, we hope that the faster the speed, the better, so choose a 16-bit interface. Of course, different TFTLCD data The number of digits is different. If the color screen is 8-bit, it is also connected to the corresponding high-order 8-bit or low-order 8-bit of 16-bit. The interface uses 16-bit to facilitate compatibility with other color screens. Figure 38.1.2 also lists the interface of the touch screen chip. We will not introduce much about the touch screen in this chapter, and will be introduced in detail in the following chapters. The 80 parallel port of the module has the following signal lines:
CS: TFTLCD chip select signal.
WR: Write data control to TFTLCD.
RD: read data control from TFTLCD.
RS: command/data selection (0, read and write commands; 1, read and write data).
DB[15:0]: 16-bit bidirectional data line.
RST: TFTLCD reset.
The communication timing of the 80 parallel port has been introduced before. It should be noted here that the RST signal line of the TFTLCD module is directly connected to the reset pin of the STM32F1 and is not controlled by software, which can save an IO port. So to control the display of the TFTLCD module, a total of 20 IO ports (except the touch function pins) are required.
These signal lines are the 8080 communication interface, through which STM32 communicates with the control chip to control the LCD screen. The content of communication mainly includes commands and video memory data, video memory data is the RGB565 content of each pixel; commands refer to the control instructions for the control chip, and the MCU can send command codes through the 8080 interface to control the working mode of the control chip, such as reset instructions, settings Cursor commands, sleep mode commands, etc., the specific commands are described in detail in the corresponding control chip data sheet. The write command timing diagram is shown in Figure 27-14.
Knowing the pin function and communication timing of the module, let's introduce how to make the LCD module display. Usually, TFT liquid crystal display can be realized according to the following steps:
(1) Set the IO connected between STM32F1 and TFTLCD module
To make the TFTLCD module display, first initialize the IO port that the TFTLCD module connects to the STM32F1 to control the TFTLCD. Here we use the FSMC using the STM32F1, and the FSMC will be introduced to you in below blog.
(2) Initialize the TFTLCD module (write a series of setting values)
Initialize the IO port, and then configure the TFTLCD. The first is to reset the LCD. Since the reset pin of the module is connected to the STM32F1 reset, just press the reset button of the development board, and then the initialization sequence, that is, to The LCD controller writes a series of setting values (such as RGB format, LCD display orientation, gamma calibration, etc.). This part of the code is generally provided by the LCD manufacturer.
(3) Write the content to be displayed into the TFTLCD module
This step needs to be implemented according to: set coordinates → write GRAM command → write GRAM, but this step is only a point processing. If we want to display characters or numbers, we must use this step multiple times to achieve the display of characters or numbers. For the purpose of numbers, we generally design a function to encapsulate these processes (to realize the display of characters or numbers), and then just call this function to realize the display of characters or numbers.
Emulate 8080 interface timing using FSMC of STM32.
The 8080 communication interface timing of the R61509V3 control chip can be simulated by STM32 using ordinary I/O interfaces, but this is too inefficient. STM32 provides a special control method - using the FSMC interface to achieve 8080 timing.
Introduction to FSMC
The STM32F1 series chips use the FSMC peripheral to manage the extended memory. FSMC is the abbreviation of Flexible Static Memory Controller, which is translated into flexible static memory controller. It can be used to drive memory including SRAM, NOR FLASH and NAND FLSAH types.
but cannot drive dynamic memory such as SDRAM. In the STM32F429 series controller, it has FMC peripherals and supports controlling SDRAM memory.
Since the FSMC peripheral can be used to control the extended external memory, the operation of the MCU on the LCD screen is actually to write the display data into the video memory, which is very similar to the control memory, and the communication timing of the 8080 interface can completely use the FSMC peripheral. Therefore, it is very suitable to use the FSMC to control the LCD screen.
The structure of the FSMC peripheral is shown in Figure 6
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| Fig 6.FSMC Block Diagram |
On the right side of the block diagram are the control pins related to the FSMC peripherals. Since there are some different pins when controlling different types of memory, it seems that there are a lot of them. The address line FSMC_A and data line FSMC_D are shared by all controllers. of. The specific GPIO ports and pin numbers corresponding to these FSMC pins can be found in the "STM32F103 Specifications" and are listed here Fig 7.
The FSMC of STM32F1 divides external devices into 2 categories: NOR/PSRAM devices, NAND/PC card devices. They share signals such as the address data bus, but have different CSs to distinguish different devices. In the experiment in this chapter, we use the NOR/PSRAM memory controller part of the FSMC, that is, use the TFTLCD as a SRAM device. Why can TFTLCD be used as a SRAM device? First of all, we need to understand the interface signals of the NOR/PSRAM memory controller.
The interface signal functions are as follows:
It can be seen from the above figure that the control of external SRAM generally includes: address line (such as A0~A25), bidirectional data line (such as D0~D15), write signal (NWE), read signal (NOE), chip select signal (NE) [x]), and UB/LB signals if the SRAM supports byte control. The signals of TFTLCD were introduced in the previous section, including: RS, DB0-DB15, WR, RD, CS, RST, etc., among which the only ones that need to be used when operating the LCD are: RS, DB0-DB15, WR , RD, CS. In this way, their operation interface signals are completely similar, the only difference is that TFTLCD has RS signal, but no address signal.
TFTLCD determines whether the transmitted data is data or command through the RS signal, which can be understood as an address signal in essence. For example, if we connect RS to A0, then when the FSMC controller writes address 0, it will make A0 become 0, For TFTLCD, it is a write command. When FSMC writes address 1, A0 will become 1. For TFTLCD, it is to write data. In this way, data and commands are distinguished, and they are actually two consecutive addresses corresponding to SRAM operations. Of course, RS can also be connected to other address lines. Our STM32F1 development board connects RS to A10.
Knowing that TFTLCD can be used as a SRAM device, let's take a look at the external device address mapping of FSMC. From the perspective of FSMC, the external memory is divided into 4 fixed-size storage areas (Bank), and the size of each storage area is 256 MB for a total of 1GB of space. As shown in Figure 8
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| Fig 8. Memory Storage |
The experiment in this chapter uses Bank1, so we only explain this storage area. For other areas, you can refer to "STM32F10x Manual"-19 Flexible Static Memory Controller (FSMC) chapter.
Memory area 1 can connect up to 4 NOR Flash or PSRAM memory devices. This memory area is divided into 4 NOR/PSRAM areas with 4 dedicated chip select signals. Banks 2 and 3 are used to connect NAND Flash devices (one device per bank). Storage area 4 is used to connect PC Card devices. For each memory area, the type of memory to be used is defined by the user in the configuration registers. The FSMC Bank configuration registers of STM32F1 are shown in Figure 38.1.2.3:
The FSMC memory block 1 (Bank1) of STM32F1 is divided into 4 areas, each area manages 64M bytes of space, and each area has independent registers to configure the connected memory. The 256M byte space of Bank1 is addressed by 28 address lines (HADDR[27:0]). Here HADDR is the internal AHB address bus, where HADDR[25:0] comes from the external memory address FSMC_A[25:0], and HADDR[26:27] addresses 4 areas. As shown in Figure 38.1.2.4:
In this chapter, we use the fourth area of Bank1, that is, the starting address is 0X6C000000. Pay special attention to HADDR[25:0] here, HADDR[25:0] contains the external memory address. Since HADDR is a byte address, and the memory is not all addressed by bytes, the actual address sent to the memory will be different depending on the data width of the memory, as shown in the following figure:
(1) For 16-bit wide external memory, FSMC will internally use HADDR[25:1] to generate the external memory address FSMC_A[24:0]. Regardless of the width of the external memory (16-bit or 8-bit), FSMC_A[0] should always be connected to the address line A[0] of the external memory.
If the width of the external memory is 8 bits, the FSMC will use the internal HADDR[25:0] address to address the external memory FSMC_A[25:0].
Please pay special attention here, if the width of the external memory is 16 bits, the FSMC will use the internal HADDR[25:1] address as the addressing address FSMC_A[24:0] for the external memory, which is equivalent to shifting one bit to the right , which will be used when we set the A10 address later. FSMC_A[0] should be connected to external memory address A[0] regardless of whether the external memory is 16-bit or 8-bit wide.
In addition, the setting of HADDR[27:26] does not require our intervention. For example, when you choose to use the third area of Bank1, that is, use FSMC_NE3 to connect external devices, it corresponds to HADDR[27:26] =10, all we have to do is to configure the register group corresponding to the third area to adapt to the external device. Each bank configuration register of FSMC is listed in Figure 38.1.2.3 above.
For the NOR FLASH controller, it is mainly set through the FSMC_BCRx, FSMC_BTRx and FSMC_BWTRx registers (where x=1~4, corresponding to 4 areas). Through these three registers, you can set the timing parameters for FSMC to access external memory, which broadens the speed range of optional external memory.
FSMC's NOR FLASH controller supports both synchronous and asynchronous burst access modes. When the synchronous burst access mode is selected, the FSMC divides the HCLK (system clock) frequency and sends it to the external memory as the synchronous clock signal FSMC_CLK. There are 2 time parameters to be set at this time: ① the frequency division factor of HCLK and FSMC_CLK (CLKDIV), which can be divided by 2 to 16; ② the waiting delay required to obtain the first data in the synchronous burst access (DATLAT) . For asynchronous burst access mode, FSMC mainly sets three time parameters: address setup time (ADDSET), data setup time (DATAST) and address hold time (ADDHLD). FSMC integrates the signal characteristics of SRAM/ROM, PSRAM and NORFlash products, and defines 4 different asynchronous timing models. When selecting different timing models, you need to set different timing parameters, as listed in Figure 38.1.2.5:
In the actual expansion, the timing model is determined according to the characteristics of the selected memory, so as to determine the calculation relationship between each time parameter and the memory read/write cycle parameter index; Calculate the time parameters required by the FSMC, so as to reasonably configure the time parameter registers. In this chapter, we use asynchronous mode A (ModeA) to control the TFTLCD. The read operation sequence of mode A is shown in Figure Fig10.
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| Fig 10. SRAM Asynchronous mode A |
Mode A supports independent read and write timing control, which is very useful for us to drive TFTLCD, because TFTLCD is generally slower when reading, but can be faster when writing, if the same timing is used for reading and writing, then only Based on the read timing, the writing speed will be slowed down, or when reading data, reconfigure the delay of the FSMC, and when the read operation is completed, configure the writing back timing, which will not reduce the writing speed. , but frequent configuration is more troublesome. If there is an independent read and write timing control, then we only need to configure it during initialization, and then we don't need to configure it again, which can meet the speed requirements without frequent configuration changes. The write operation timing of Mode A is shown in Figure 11.
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| Fig 11. SRAM Synchronous mode A |
ADDSET and DATAST in the read and write timing of mode A are set by different registers. Due to space limitations, this chapter does not introduce FSMC related registers. You can refer to "STM32F10x Chinese Reference Manual"-19 Flexible Static Memory Controller (FSMC) chapter register content, which has a detailed explanation. However, here is a popular science for you. In the register definition of the standard library, there are no separate registers such as FSMC_BCRx, FSMC_BTRx, FSMC_BWTRx, etc., but some combination of them.
FSMC_BCRx and FSMC_BTRx are combined into the BTCR[8] register group, and their corresponding relationship is as follows:
BTCR[0] corresponds to FSMC_BCR1, BTCR[1] corresponds to FSMC_BTR1
BTCR[2] corresponds to FSMC_BCR2, BTCR[3] corresponds to FSMC_BTR2
BTCR[4] corresponds to FSMC_BCR3, BTCR[5] corresponds to FSMC_BTR3
BTCR[6] corresponds to FSMC_BCR4, BTCR[7] corresponds to FSMC_BTR4
FSMC_BWTRx is combined into BWTR[7], and their correspondence is as follows:
BWTR[0] corresponds to FSMC_BWTR1, BWTR[2] corresponds to FSMC_BWTR2,
BWTR[4] corresponds to FSMC_BWTR3, BWTR[6] corresponds to FSMC_BWTR4,
BWTR[1], BWTR[3] and BWTR[5] are reserved and not used.
The interior of FSMC is still relatively complicated. If you don't understand it, you can put it down temporarily, because we are using library function development, which can be used with simple configuration.
FSMC configuration steps
Next, we will introduce how to use library functions to configure FSMC. This is also necessary to understand when writing programs. The specific steps are as follows: (The FSMC related library functions are in stm32f10x_fsmc.c and
stm32f10x_fsmc.h file)
(1) FSMC initialization
The initialization of FSMC mainly configures three registers, FSMC_BCRx, FSMC_BTRx, and FSMC_BWTRx. The firmware library provides three initialization functions to configure these registers. FSMC initialization library function
as follows:
FSMC_NORSRAMInit();
FSMC_NANDInit();
FSMC_PCCARDInit();
These three functions are used to initialize 4 types of memory respectively. Here it is good to judge the correspondence according to the name. The same function FSMC_NORSRAMInit() is used to initialize NOR and SRAM. So the FSMC initialization function we use later is FSMC_NORSRAMInit(). The initialization function prototype is:
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
This function has only one parameter, which is a structure pointer variable. The structure type is FSMC_NORSRAMInitTypeDef, and there are many member variables in it, because there are many configuration items related to FSMC. Below we briefly introduce its members:
typedef struct
{
uint32_t FSMC_Bank;
uint32_t FSMC_DataAddressMux;
uint32_t FSMC_MemoryType;
uint32_t FSMC_MemoryDataWidth;
uint32_t FSMC_BurstAccessMode;
uint32_t FSMC_AsynchronousWait;
uint32_t FSMC_WaitSignalPolarity;
uint32_t FSMC_WrapMode;
uint32_t FSMC_WaitSignalActive;
uint32_t FSMC_WriteOperation;
uint32_t FSMC_WaitSignal;
uint32_t FSMC_ExtendedMode;
uint32_t FSMC_WriteBurst;
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
}FSMC_NORSRAMInitTypeDef;
From this structure, we can see that there are 13 member variables of basic type (unit32_t) in front. These 13 parameters are used to configure the chip select control register FSMC_BCRx. The last two
FSMC_NORSRAMTimingInitTypeDef Pointer type member variable. As we mentioned earlier, FSMC has read timing and write timing, so here are the parameters used to set the read timing and write timing, that is to say, these two parameters are used to configure the registers FSMC_BTRx and FSMC_BWTRx, we will later explained. Let's take a look at these members:
FSMC_Bank: used to set the used memory block label and area code. In this chapter, we are using memory block 1 and area code 4, so the selected value is FSMC_Bank1_NORSRAM4.
FSMC_DataAddressMux: It is used to configure whether the data line and address line of FSMC are multiplexed. FSMC supports two modes of data and address line multiplexing or non-multiplexing. In non-multiplexing mode, 16-bit data lines and 26-bit address lines are used separately; in multiplexing mode, the lower 16-bit data/address lines are multiplexed, which is only valid for NOR and PSRAM. In multiplexed mode, address latches are recommended to distinguish data from addresses. In this experiment, FSMC is used to simulate 8080 timing, and only one address line A10 is used to provide the RS signal of 8080, so it does not need to be multiplexed, that is, set to FSMC_DataAddressMux_Disable.
FSMC_MemoryType: used to set the external memory type of FSMC, the optional types are NOR FLASH mode, PSARM mode and SRAM mode. We use TFTLCD as SRAM here, so the selected value is FSMC_MemoryType_SRAM.
FSMC_MemoryDataWidth: used to set the data width of the FSMC interface, you can choose 8-bit or 16-bit, here we are 16-bit data width, so the selected value is FSMC_MemoryDataWidth_16b.
FSMC_WriteOperation: used to configure the write operation enable, if the write operation is disabled, the FSMC will not generate a write sequence, but the data can still be read from the memory. This experiment needs to write data to the TFTLCD, so the write enable is required, and the configuration is FSMC_WriteOperation_Enable (write enable).
FSMC_ExtendedMode: Used to configure whether to use extended mode. In extended mode, read timing and write timing can use independent timing mode. For example, mode A is used for read timing, and mode B is used for write timing. These A, B, C, and D modes are actually not very different. The main reason is that when data/address line multiplexing is used, the timing generated by the FSMC signal is different.
FSMC_BurstAccessMode: Used to configure the access mode. FSMC access to memory is divided into asynchronous mode and burst mode (synchronous mode). In the asynchronous mode, a definite address needs to be generated each time the data is transferred, while the burst mode can provide an address at the beginning, and then write the data in groups continuously. This lab uses the asynchronous mode FSMC_BurstAccessMode_Disable.
FSMC_WaitSignalPolarity (configure wait signal polarity), FSMC_WrapMode (configure whether to use non-alignment), FSMC_WaitSignalActive (configure when the wait signal is generated),
FSMC_WaitSignal (configure whether to use wait signal), FSMC_WriteBurst (configure whether to allow burst write operation), these members need to be configured after burst mode is enabled. This experiment uses asynchronous mode, so the parameters of these members have no meaning.
FSMC_ReadWriteTimingStruct and FSMC_WriteTimingStruct: used to set the read and write timing. Both variables are of FSMC_NORSRAMTimingInitTypeDef structure pointer type. These two parameters are used to initialize the chip select control register FSMC_BTRx and the write operation timing control register FSMC_BWTRx respectively during initialization.
The FSMC_NORSRAMTimingInitTypeDef structure is as follows:
typedef struct
{
uint32_t FSMC_AddressSetupTime;//Address setup time
uint32_t FSMC_AddressHoldTime;//Address hold time
uint32_t FSMC_DataSetupTime;//Data setup time
uint32_t FSMC_BusTurnAroundDuration;//Bus recovery time
uint32_t FSMC_CLKDivision;//Clock frequency division
uint32_t FSMC_DataLatency;//Data retention time
uint32_t FSMC_AccessMode;//Access mode
}FSMC_NORSRAMTimingInitTypeDef;
These members are mainly used to design the address establishment and hold time, data establishment time and other configurations. These times are obtained by the frequency division of the member clock by HCLK. The frequency division value is set in the member FSMC_CLKDivision (clock frequency division), where FSMC_AccessMode (access mode) Mode) member settings are only valid when the extended mode is enabled, and after the extended mode is enabled, the read timing and write timing settings can be independent. In this experiment, we need different read and write speeds, so the extended mode is turned on and different values are set for the parameter FSMC_DataSetupTime. This structure actually operates on the FSMC_BTRx and FSMC_BWTRx registers. You can check the register description in the Chinese Reference Manual.
The timing settings in this experiment are set according to the data sheet of R61509V3. When debugging, you can set these values to be larger first, and then slowly approach the minimum value required by the data sheet, which will achieve better results. The parameter setting of the timing has a certain influence on the display effect of the LCD.
After understanding the function of structure members, you can configure it. The experimental configuration code in this is as follows:
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
FSMC_NORSRAMTimingInitTypeDef FSMC_ReadNORSRAMTiming;
FSMC_NORSRAMTimingInitTypeDef FSMC_WriteNORSRAMTiming;
FSMC_ReadTimingInitStructure.FSMC_AddressSetupTime = 0x01;//Address setup time (ADDSET) is 2 HCLK 1/36M=27ns
FSMC_ReadTimingInitStructure.FSMC_AddressHoldTime = 0x00;//Address hold time (ADDHLD) mode A is not used
FSMC_ReadTimingInitStructure.FSMC_DataSetupTime = 0x0f;//The data storage time is 16 HCLKs, because the reading speed of the LCD driver IC cannot be too fast, especially for the 1289 IC.
FSMC_ReadTimingInitStructure.FSMC_BusTurnAroundDuration = 0x00;
FSMC_ReadNORSRAMTiming.FSMC_CLKDivision = 0x00;
FSMC_ReadNORSRAMTiming.FSMC_DataLatency = 0x00;
FSMC_ReadNORSRAMTiming.FSMC_AccessMode = FSMC_AccessMode_A;//Mode A
FSMC_WriteNORSRAMTiming.FSMC_AddressSetupTime =0x00;//Address setup time (ADDSET) is 1 HCLK
FSMC_WriteNORSRAMTiming.FSMC_AddressHoldTime = 0x00;//ground
This part of the content FMSC Programming using CubeMX and TouchGFX AND can seen https://www.microcontrollertutorials.com/2022/07/stm32-graphics-hardware-foundation.html
